1. Field of the Invention
The present invention relates to data communication, and more particularly, to a circuit and method for recovering data and a clock signal in a receiver in a data transmission system.
2. Description of the Related Art
Conventionally, phase-locked loops (PLL) are widely used to recover clock signals from data received at a receiving end of a data communication or transmission system and then extract and recover the data using the recovered clock signals. Clock signal and data recovery circuits like PLLs are required to have a short locking time and low jitter and skew so as to reduce a bit error rate (BER).
To meet these demands, data recovery circuits having a dual loop structure including a frequency-locked loop (FLL) and a phase-locked loop (PLL) are generally used. Data recovery circuits having such a structure perform frequency locking of signals through the use of the frequency-locked loop first and then perform phase locking of signals through the use of the phase-locked loop.
However, the conventional data recovery circuits have a few drawbacks. Specifically, the frequency-locked loop (FLL) or the phase-locked loop (PLL) uses a voltage controlled oscillator (VCO), which introduces significant noise caused by power supplies or heat. The noise of the voltage controlled oscillator VCO cannot be removed from the output of the phase-locked loop and acts as jitter. This problem can be slightly alleviated by decreasing the gain of the phase-locked loop, but if the gain of the phase-locked loop is reduced, the locking time increases considerably.
In addition, in order to decrease the locking time in the data recovery circuit having the dual loop structure, the frequency range of the phase-locked loop having a low response speed must be reduced by increasing the resolution of the frequency-locked loop and reducing errors, which may occur during frequency locking, to the minimum.
To solve the above-described problems, it is a first object of the present invention to provide a data recovery circuit and method which simultaneously reduce jitter and locking time.
Accordingly, to achieve the first object, there is provided a data recovery circuit including a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back into the frequency-locked loop in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the internal clock signal is frequency-locked with the input signal. The locking detector determines whether not the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal and locks the phase of the internal clock signal with the phase of the input signal and generates a recovery locking signal. The data determination circuit receives the recovery locking signal as a clock signal and receives the input signal in response to the clock signal, and outputs the input signal as output data.
In one embodiment, the frequency-locked loop includes a frequency detector, a charge pump, a low-pass filter and an oscillator. The frequency-locked loop compares the frequency of the input signal with the frequency of the internal clock signal, detects the frequency difference between the input signal and the internal clock signal, and generates the frequency locking signal. The charge pump is charged or discharged in response to the output of the frequency detector. The low-pass filter removes a high-frequency component from the output signal of the charge pump and generates a control voltage. The oscillator generates the internal clock signal in response to the control voltage, compares the frequency of the internal clock signal with the frequencies of the input signal at rising and falling edges, and detects the frequency difference between the internal clock signal and the input signal.
In one embodiment, a lock window of the locking detector has hysteresis characteristics in order to prevent the frequency-locked loop from deviating from a locked state.
In one embodiment, the delay-locked loop includes a delay line, a middle delay line, a phase detector and a shift register. The delay line receives the internal clock signal, delays the internal clock signal for a predetermined time, and generates the recovery locking signal. The middle delay line receives the input signal, delays the input signal for a predetermined time, and generates a middle input signal. The phase detector compares the phase of the middle input signal with the phase of the recovery locking signal, detects the phase difference between the middle input signal and the recovery locking signal, and generates at least one of a first move signal and a second move signal. The resister controls the delay time of the delay line in response to the at least one of the first and second move signals. In one embodiment, the phase detector compares the phase of the recovery locking signal with the phases of the middle input signal at rising and falling edges and detects the phase difference between the recovery locking signal and the middle input signal. In one embodiment, the phase detector includes a first flip-flop which receives the middle input signal as a clock signal, receives the recovery locking signal in response to the clock signal, and outputs the recovery locking signal; a first buffer which delays the recovery locking signal for a predetermined time; a second flip-flop which receives the middle input signal as a clock signal, receives the output signal of the first buffer in response to the clock signal, and outputs the output signal of the first buffer; a first logical AND means which performs a logical AND operation on the output signal of the first flip-flop and the output signal of the second flip-flop and generates the first move signal; and a second logical AND means which performs a logical AND operation on an inverted signal of the output signal of the first flip-flop and an inverted signal of the output signal of the second flip-flop and generates the second move signal. The first buffer can have the same delay time as a unit delay device existing in the delay line.
In one embodiment, the first move signal reduces the delay time of the delay line by controlling the shift register, and the second move signal increases the delay time of the delay line by controlling the shift register. In another embodiment, the first move signal increases the delay time of the delay line by controlling the shift register and the second move signal decreases the delay time of the delay line by controlling the shift register.
In another aspect of the invention, there is provided a data recovery method of a data recovery circuit including a frequency-locked loop and a delay-locked loop, the method including: (a) locking the frequency of an internal clock signal fed back into the frequency-locked loop in response to an input signal with the frequency of an input signal and generating a frequency locking signal representing that the internal clock signal is frequency-locked with the input signal; (b) determining whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generating a phase control signal; receiving the input signal and the internal clock signal in response to the phase controlled signal and locking the phase of the internal clock signal with the phase of the input signal and generating a recovery locking signal, locking the phase of the internal clock signal with the phase of the input signal in response to the input signal and the internal clock signal and generating a recovery locking signal; and (d) receiving the recovery locking signal as a clock signal, receiving the input signal in response to the clock signal, and outputting the input signal as output data.
Accordingly, the data recovery circuit and method according to the present invention are capable of simultaneously reducing jitter and locking time.